--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   17:50:35 03/21/2012
-- Design Name:   
-- Module Name:   Z:/Documents/workspace/Home/hayes2vhdl/references/uart2bus/trunk/vhdl/uart2Bus/uartTop_tb.vhd
-- Project Name:  uart2Bus
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: uartTop
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
 
ENTITY uartTop_tb IS
END uartTop_tb;
 
ARCHITECTURE behavior OF uartTop_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT uartTop
    PORT(
         clr : IN  std_logic;
         clk : IN  std_logic;
         serIn : IN  std_logic;
         serOut : OUT  std_logic;
         txData : IN  std_logic_vector(7 downto 0);
         newTxData : IN  std_logic;
         txBusy : OUT  std_logic;
         rxData : OUT  std_logic_vector(7 downto 0);
         newRxData : OUT  std_logic;
         baudFreq : IN  std_logic_vector(11 downto 0);
         baudLimit : IN  std_logic_vector(15 downto 0);
         baudClk : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal clr : std_logic := '0';
   signal clk : std_logic := '0';
   signal serIn : std_logic := '0';
   signal txData : std_logic_vector(7 downto 0) := (others => '0');
   signal newTxData : std_logic := '1';
   signal baudFreq : std_logic_vector(11 downto 0) := x"480";
   signal baudLimit : std_logic_vector(15 downto 0) := x"3889";

 	--Outputs
   signal serOut : std_logic;
   signal txBusy : std_logic;
   signal rxData : std_logic_vector(7 downto 0);
   signal newRxData : std_logic;
   signal baudClk : std_logic;

   -- Clock period definitions
   constant clk_period : time := 40 ns;	
	
	type uart_string_t is array (0 to 3) of std_logic_vector(7 downto 0); 
	constant uartCmd : uart_string_t := (x"41", x"42", x"43", x"44");

	signal index :integer := 0;
	 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: uartTop PORT MAP (
          clr => clr,
          clk => clk,
          serIn => serIn,
          serOut => serOut,
          txData => txData,
          newTxData => newTxData,
          txBusy => txBusy,
          rxData => rxData,
          newRxData => newRxData,
          baudFreq => baudFreq,
          baudLimit => baudLimit,
          baudClk => baudClk
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

	-- Just assign serial output to serial input
   serial_process :process
   begin
		wait until (rising_edge(baudClk)); serIn <= serOut;
	end process;


	-- Put next symbol to TX module
	tx_data_process :process
	begin
		-- Put next byte to uart
		txData <= uartCmd(index);
		
		-- Produce new Tx data available signal
		wait until (rising_edge(baudClk)); newTxData <= '1';
		wait for 9 us;
		wait until (rising_edge(baudClk)); newTxData <= '0';

		-- Wait for new Rx data available signal
		wait until (falling_edge(newRxData));

		-- Inctement array index
		index <= index + 1;
		if (index = uartCmd'high) then
			index <= 0;
		end if;
	end process;
	
	
   -- Stimulus process
   stim_proc: process
   begin		
		-- Reset statement
		clr <= '1';
      wait for 100 ns;	
		clr <= '0';
		wait for 10 ns;

		wait;
   end process;

END;
